For an analog circuit, an analog switching circuit with a complementary metal oxide semiconductor (CMOS) may be used. It is, however, structurally difficult to use the CMOS at high voltage. Use of a structure able to withstand high voltage dynamically raises manufacturing cost.
Therefore, a laterally diffused metal oxide semiconductor (LDMOS) or an Offset metal oxide semiconductor field effect transistor (MOSFET) may be used to create an analog switching circuit which is used in a circuit at higher voltage. The LDMOS and the Offset MOSFET are structurally able to withstand relatively high voltage between a drain and a gate in comparison with a CMOS. The Offset MOSFET is a MOSFET which has a longer distance between the drain and the gate than the CMOS. However, it is necessary to protect a portion between the source and gate of the LDMOS or the Offset MOSFET to prevent the application of high voltage.
Therefore, for example, in the case of using a p-channel LDMOS (PLDMOS) for a switch, a zener diode may be arranged between the source and the gate to protect the portion between the source and the gate and then a resistor may be arranged between the source and the gate to control current flowing through the resistor in order to control the on/off status of the switch. In this method, however, when the control current flows, the ON resistance of the PLDMOS for use in the switch decreases the source-side voltage relative to the drain-side voltage of the PLDMOS. Accordingly, if it is required that the drain-side voltage equals the source-side voltage, it is inappropriate to use such a switching circuit.
For example, U.S. Pat. No. 7,030,591 discloses a configuration for a control with a MOS, but does not describe the problem which occurs when using an LDMOS or an Offset MOSFET for an analog switching circuit.